Area-efficient designs for modern microprocessors, DSP's (Digital Signal Processors), SoC's (System-on-Chip) in wearables, IoTs (Internet-of-Things), smartphones, tablets, laptops, and servers, etc., are increasingly becoming a critical factor due to the following requirements: reducing silicon cost, decreasing PCB (Printed Circuit Board) footprint, improving time-to-market (TTM), and slower scaling cadence of process technology node. These requirements all need to be met while meeting the stringent frequency and/or performance targets and power/leakage budgets.
A major component of the power dissipation in digital systems is due to charging and discharging load capacitance of circuit nodes, otherwise known as dynamic power. In today's clocked synchronous systems—microprocessors, DSP's, and SoC's in smartphones, tablets, laptops, and servers, a large percentage of the overall power dissipation (e.g., greater than 30%) is in the clock grid and final sequential load.